1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile memory device and a method of producing the same.
2. Description of the Related Art
In the recent highly-sophisticated information society, there has been a demand for further improvement in performance of a solid-state memory device formed by using semiconductor integrated circuit technology. In particular, as the computational capacity of a micro processing unit (MPU) is improved, memory capacities of a computer and an electronic apparatus have been increased. Unlike a magnetic and a magneto-optical storage device such as a hard disk and a laser disk, the solid-state memory device does not have a physically driven portion therein. The solid-state memory device, therefore, has a high mechanical strength and can be highly integrated based on the semiconductor manufacturing technology. For this reason, the solid-state memory device has been used not only as a temporary storage device (cache) and as a main storage device (main memory) for a computer and a server, but also as an external storage device (storage memory) for a large number of mobile apparatus and household electrical appliances and has led to the development of a market on the order of several tens of billions of dollars at present.
Such solid-state memory devices are classified into three types according to their principle of operation: a static random access memory (SRAM), a dynamic random access memory (DRAM) and an electrically erasable and programmable read only memory (EEPROM) which is represented by a flash memory device. The SRAM is the fastest among the above memory devices; however, it cannot hold information while power is turned off, and requires a large number of transistors to store one bit, which is not suitable for providing a large capacity. For this reason, the SRAM is mainly used as cache in an MPU. The DRAM requires a refresh operation and operates slower than the SRAM; however, it can easily be integrated at a lower unit cost for one bit. Therefore, the DRAM is mainly used for a main memory of a computer and a household electrical appliance. On the other hand, the EEPROM is a non-volatile memory device capable of holding information even while the power supply is turned off. The EEPROM is slower in writing and erasing information than the above devices and requires relatively large electric power, and therefore, it is mainly used for memory storage.
Because the market for mobile communication equipment has rapidly grown in recent years, there has been a demand for the development of DRAM-compatible solid-state memory devices which are faster and capable of operating at a lower power consumption, and there has been demand for even non-volatile solid-state memory devices having features of both DRAM and EEPROM. For such a next-generation solid-state memory device, an attempt has been made to develop a resistive random access memory (RRAM) using a variable resistor and a ferroelectric RAM (FeRAM) using a ferroelectric substance. In addition, one of the promising candidates for a non-volatile memory device which is faster and capable of operating at a lower power consumption is a phase change random access memory (PRAM) using a phase change material. The phase change random access memory writes information at a speed as high as about 50 ns and has the advantage that the memory can be easily integrated because of its simple configuration.
The phase change memory device is a non-volatile memory device having a structure in which a phase change material is sandwiched between two electrodes. The memory device is selectively operated by an active element connected in series in a circuit. The active element includes, for example, a metal-oxide-semiconductor (MOS) transistor, a junction diode, a bipolar transistor and a Schottky barrier diode. FIG. 21 is a schematic cross section of a general vertical phase change memory device. FIG. 22 is a schematic cross section of a vertical phase change memory cell in which a general select MOS transistor is arranged. The vertical phase change memory device has a structure in which two electrodes in contact with the phase change material are arranged perpendicularly (vertically) with respect to the material. FIG. 23 is a circuit configuration of one cell corresponding to FIG. 22. A memory cell array is formed by cells arranged in a lattice configuration and each cell is made up of the combination of the phase change memory device and an selective active element (or MOS transistor in case of FIG. 23). This structure is characterized such that the cell can be easily and highly integrated and the cell integration techniques for the DRAM can be used because the cell is similar in configuration to the DRAM. As the case may be, the configuration of memory cell peripheral circuits and the memory cell can be further devised to form a memory cell without an selective active element.
Storage and erasure of data in the phase change memory device are performed by using thermal energy to cause a transition between two or more solid phases, such as (poly) crystal state and amorphous state in a phase change material. The transition between the crystal state and the amorphous state is identified as a change in a resistance value from a circuit connection through the electrodes. To apply thermal energy to the phase change material, an electric pulse (voltage or current pulse) is applied between the electrodes to heat the phase change material itself using Joule heating. At this point, for example, an electric pulse of a large current is applied to a phase change material in a crystal state for a short time to heat the phase change material to a high temperature near its melting point and then quench it, thereby turning the phase change material into an amorphous state (this state is called “resetting state”). This operation is generally referred to as resetting operation. On the other hand, in the resetting state, an electric pulse of a current smaller than in the resetting operation is applied to the phase change material for a relatively long time to heat the phase change material to the temperature of crystallization, thereby turning the phase change material into a crystal state (this state is called “setting state”). This operation is referred to as setting operation in contrast with the resetting operation.
Since the phase change memory device is activated by the selective active element, information needs to be rewritten within the driving current capacity of the selective active element. However, in a phase change memory device produced in the currently latest lithography technology, it is difficult to keep a current value required for the resetting operation within the driving current capacity of the selective active element, while maintaining the cell integration level as much as the DRAM.
It is effective to reduce (scale) the phase change area of the phase change material for enabling a vertical phase change memory device to switch at low electric power (current). For example, it is desirable to fully cover a lower (or an upper) electrode with a phase-change (or changed) area or to cause all paths of current flowing into the phase change random material to always pass the phase change area, in order to identify the transition of states of the phase change material as change in a resistance value when the resetting operation is performed from the setting state. The phase change area refers to an area where a phase change actually occurs. The entire volume of the formed phase change material does not always need to be the phase change area.
In the phase change memory device illustrated in FIG. 20, the phase change area in the phase change material is formed in the vicinity of an interface between the phase change material and a lower electrode where the highest current density appears at the time of writing information. In other words, heat is generated around the portion where the phase change material is in contact with the lower electrode and that portion mainly exhibits phase change. For this reason, reducing the contact cross section of the lower electrode in contact with the phase change material helps to reduce the phase change area and power consumption at the time of rewriting information. When self-joule heating occurs in the phase change material, the most of the heat will be dissipated in the electrode. From these standpoints, it is effective to reduce the contact cross section of the electrode in contact with the phase change material and the cross section of the electrode itself in terms of suppressing heat radiation from the phase change material and efficiently causing the phase change.
However, in the typical semiconductor manufacturing process, the dimension of the electrode connected to the phase change material is determined by the minimum processing dimension in a lithography processing, so it is difficult to reduce the dimension as small as the process trend or lower. The minimum processing dimension is the minimum formable processing linewidth dimension or the minimum formable processing space dimension which is determined by a manufacturing process, such as resolution capability in photolithography and processing capability in etching respectively and is in the order of 70 mm at present.
As described in Patent Document 1 and non-Patent Document 1, there has been presently proposed a technique in which a thin film electrode material is deposited on a trench structure (U shaped trench) and a protective insulating material and an insulating material are deposited thereon and planarization is performed, thereby forming a small electrode independently of lithography technique. FIGS. 24 and 25 are schematic diagrams illustrating a vertical cross section of an electrode in its forming step. As illustrated in FIG. 24, a lower electrode material and a protective insulating material are deposited on a trench structure and an insulating material is further deposited thereon by an SOG method. As illustrated in FIG. 25, planarization is performed using a CMP method, thereby forming a phase change memory device illustrated in FIG. 1. The method is capable of forming a lower electrode with a micro-cross section only using a relatively easy processing.
The necessity of forming such a small electrode is not limited to a phase change memory device. Patent Document 2 describes that the physical property change area of a variable resistor needs to be reduced in an RRAM.
The RRAM is a non-volatile memory element making use of the fact that a resistance change material exhibits resistance switching by applying a voltage pulse, and refers to all materials exhibiting the resistance switching based on a principle other than a resistance change caused by phase change such as the phase change memory element.    [Patent Document 1] US2003/0193063 A1    [Patent Document 2] Japanese Patent Laid-Open No. 2007-180474    [Non-Patent Document 1] F. Bedeschi et al. IEEE J. Solid-State Circuit 40 (2005)1557.
As described above, reduction in power consumption (particularly, current consumption) at the time of rewriting information in a phase change memory device is an essential issue to be resolved for an actual mass production. In general, it is known that the reduction of a contact area between the phase change material and the electrode reduces not only heat radiation from the electrode, but also power consumption (current) because the resistance switching can be achieved only in a small phase change area. However, in the manufacturing method of the vertical phase change memory device mainly based on conventional lithography processing techniques, the cross section of the electrode is determined by the minimum processing dimension in the lithography processing technique at the time of forming the electrode perpendicularly with respect to the phase change material (or with respect to a substrate), so that the improvement of performances of a semiconductor manufacturing apparatus is essential to reduce power consumption (current).
At present, as a method of solving the above issue, Patent Document 1 and non-Patent Document 1 have proposed a method in which an ultrathin electrode material is deposited on a trench structure. FIG. 1 is a schematic cross section of a vertical phase change memory device produced by the proposed method. The use of the trench structure allows a contact area to be reduced to approximately one fifth of an area in the related art. However, in the method, as illustrated in the three dimensional schematic diagram in the vicinity of the electrode in FIG. 2, while electrode width “d” in the X direction in the figure can be reduced to approximately 10 nm, electrode width “w” can be reduced only to the minimum processing dimension in the lithography processing because a lithography technique is used for processing in the Y direction in the figure.